1. Field of the Invention
The present invention relates to a metal silicide layer of a semiconductor device, to a method of forming the same, and to semiconductor devices comprising such a metal silicide layer, and more particularly, to a metal silicide layer of a semiconductor device which prevents or at least minimizes agglomeration of metal silicide and has a property of improved thermal stability, to a method of forming the same, and to semiconductor devices comprising such a metal silicide layer.
2. Description of the Related Art
Generally, a metal silicide layer is formed as part of a semiconductor device in order to obtain the properties of a low resistance active region and a low resistance gate electrode in a semiconductor device requiring a high processing speed. The metal silicide layer of the semiconductor device lowers contact resistances of the active region and the gate electrode. Such a layer is mainly formed by combining a suitable metal with silicon, to form for example titanium silicide (TiSi2), tungsten silicide (WSi2), cobalt silicide (CoSi2) or nickel silicide (NiSi2).
As the design rule of a semiconductor device is scaled down, the formation of a metal silicide layer becomes increasingly essential. On the other hand, as the design rule of the semiconductor device is scaled down, it also becomes increasingly difficult to ensure a suitable margin for forming the metal silicide layer. Accordingly, it becomes more and more difficult to perform a process of forming the metal silicide layer in the semiconductor device.
Thus, in a case where a line width of a gate electrode is reduced due to miniaturization of a semiconductor device which includes a metal silicide layer according to the prior art, it is difficult to properly form the metal silicide layer on a surface of the gate electrode because agglomeration of metal occurs such that a good metal silicide layer cannot be obtained.
Furthermore, because the metal silicide layer is typically formed on a gate electrode which is formed of n-type or p-type doped polysilicon using a high temperature thermal process in the formation of the metal silicide layer on the semiconductor device according to prior art techniques, a thermal stability property of the metal silicide layer is reduced or impaired due to migration effects occurring along a grain boundary of n-type or p-type doped polysilicon. Moreover, since the grain boundary of the polysilicon is used as a diffusion passage for metal, reliability of the gate oxide layer can also be reduced.
Because it is not necessary to perform the usual high temperature thermal process for the formation of a nickel silicide layer, such a nickel silicide layer will typically demonstrate a better stability than, for example, a cobalt silicide layer relative to a chemical characteristic such as a resistance or a phase shift. However, since agglomeration of nickel silicide often occurs during a subsequent high temperature thermal process used in completing the semiconductor device, the final nickel silicide layer may demonstrate a low thermal stability. Thus, subsequent processing of the semiconductor device performed after formation of the nickel silicide layer must be performed in a limited temperature range not exceeding a silicide formation temperature in order to prevent the agglomeration or the phase shift of the metal silicide. However, in practice, it is frequently difficult or impossible to maintain such a processing temperature restriction in a fabrication process of a semiconductor circuit in which various products are integrated.
Accordingly, applying prior art techniques may adversely affect the thermal stability of a metal silicide layer of a miniature semiconductor device, and/or may also damage other characteristics of the metal silicide layer due to an excessive processing temperature used in a subsequent thermal step in the completion of the semiconductor device. These and other problems with and limitations of the prior art are addressed in whole, or at least in part, by the present invention.